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FEATURES
s s
LTC1709 2-Phase, 5-Bit Adjustable, High Efficiency, Synchronous Step-Down Switching Regulator DESCRIPTIO
The LTC(R)1709 is a 2-phase, VID programmable, synchronous step-down switching regulator controller that drives all N-channel external power MOSFET stages in a fixed frequency architecture. The 2-phase controller drives its two output stages out of phase at frequencies up to 300kHz to minimize the RMS ripple currents in both input and output capacitors. The 2-phase technique effectively multiplies the fundamental frequency by two, improving transient response while operating each channel at a optimum frequency for efficiency. Thermal design is also simplified. An internal differential amplifier provides true remote sensing of the regulated supply's positive and negative output terminals as required in high current applications. The RUN/SS pin provides soft-start and optional timed, short-circuit shutdown. Current foldback limits MOSFET dissipaton during short-circuit conditions when overcurrent latchoff is disabled. OPTI-LOOP compensation allows the transient response to be optimized for a wide range of output capacitors and ESR values.
s s s s
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Two Ouput Stages Operate Antiphase Reducing Input Capacitance and Power Supply Noise 5-Bit VID Control (VRM 8.4 Compliant) VOUT: 1.3V to 3.5V in 50mV/100mV Steps Current Mode Control Ensures Current Sharing True Remote Sensing Differential Amplifier OPTI-LOOPTM Compensation Minimizes COUT Programmable Fixed Frequency: 150kHz to 300kHz--Effective 300kHz to 600kHz Switching Frequency 1% Output Voltage Accuracy Wide VIN Range: 4V to 36V Operation Adjustable Soft-Start Current Ramping Internal Current Foldback Short-Circuit Shutdown Timer with Defeat Option Overvoltage Soft-Latch Eliminates Nuisance Trips Low Shutdown Current: 20A Small 36-Lead Narrow (0.209") SSOP Package
APPLICATIO S
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Desktop Computers Internet/Network Servers Large Memory Arrays DC Power Distribution Systems Battery Chargers
, LTC and LT are registered trademarks of Linear Technology Corporation. OPTI-LOOP is a trademark of Linear Technology Corporation.
TYPICAL APPLICATIO
0.1F VIN RUN/SS 1.2nF ITH
S
TG1 BOOST 1 SW1
Q1
S
10F x4 35V 0.002 1H
VIN 5V TO 28V 100
0.47F
S
LTC1709
15k
BG1 PGND
Q2
EFFICIENCY (%)
SGND 5 VID BITS VID0-VID4 EAIN FBOUT SENSEIN VDIFFOUT VOS - VOS
+
SENSE1 + SENSE1 - TG2 BOOST2 SW2 BG2 INTVCC SENSE 2 + SENSE 2 -
S S S
Q3 0.47F 1H Q4 0.002 VOUT 1.3V TO 3.5V 40A
S
10F
+
COUT 1000F 4V x2
1709 TA01
+
Q1-Q4 2x FAIRCHILD FDS7760A OR SILICONIX Si4874
Figure 1. High Current 2-Phase Step-Down Converter
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Efficiency Curve
VIN = 5V VOUT = 1.6V fS = 200kHz
90
80
70
60
50 0 5 10 15 20 25 30 35 LOAD CURRENTS (A) 40 45
1709 TA01a
1
LTC1709
ABSOLUTE
(Note 1)
AXI U RATI GS
PACKAGE/ORDER I FOR ATIO
TOP VIEW RUNN/SS SENSE 1 + SENSE 1 - EAIN PLLFLTR PLLIN NC ITH SGND 1 2 3 4 5 6 7 8 9 36 NC 35 TG1 34 SW1 33 BOOST 1 32 VIN 31 BG1 30 EXTVCC 29 INTVCC 28 PGND 27 BG2 26 BOOST 2 25 SW2 24 TG2 23 AMPMD 22 VBIAS 21 VID4 20 VID3 19 VID2
Input Supply Voltage (VIN).........................36V to - 0.3V Topside Driver Voltages (BOOST 1, 2) .......42V to - 0.3V Switch Voltage (SW1, 2) .............................36V to - 5 V SENSE 1+, SENSE 2 +, SENSE 1-, SENSE 2 - Voltages ....................... (1.1)INTVCC to - 0.3V EAIN, VOS+, VOS-, EXTVCC, INTVCC, RUN/SS, AMPMD, VBIAS, ATTENIN, ATTENOUT, VID0-VID4, Voltages ...................................7V to - 0.3V Boosted Driver Voltage (BOOST-SW) ..........7V to - 0.3V PLLFLTR, PLLIN, VDIFFOUT Voltages .... INTVCC to - 0.3V ITH Voltage ................................................2.7V to - 0.3V Peak Output Current <1s(TGL1, 2; BG1, 2) .............. 3A INTVCC RMS Output Current ................................ 50mA Operating Ambient Temperature Range (Note 2) .................................................. - 40C to 85C Junction Temperature (Note 3) ............................. 125C Storage Temperature Range ................. - 65C to 150C Lead Temperature (Soldering, 10 sec).................. 300C
ORDER PART NUMBER LTC1709EG
VDIFFOUT 10 VOS - 11 VOS + 12 SENSE 2 - 13 SENSE 2 + 14
ATTENOUT 15 ATTENIN 16 VID0 17 VID1 18
G PACKAGE 36-LEAD PLASTIC SSOP
TJMAX = 125C, JA = 85C/W
Consult factory for Industrial and Military grade parts.
ELECTRICAL CHARACTERISTICS
SYMBOL VEAIN VSENSEMAX IINEAIN VLOADREG PARAMETER Regulated Feedback Voltage Maximum Current Sense Threshold Feedback Current Output Voltage Load Regulation Main Control Loop
The q denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. VIN = 15V, VRUN/SS = 5V unless otherwise noted.
CONDITIONS (Note 4); ITH Voltage = 1.2V VSENSE - = 5V (Note 4) (Note 4) Measured in Servo Loop; ITH Voltage: 1.2V to 0.7V Measured in Servo Loop; ITH Voltage: 1.2V to 2V VIN = 3.6V to 30V (Note 4) Measured at VEAIN VIN Ramping Down ITH = 1.2V; Sink/Source 5A; (Note 4) ITH = 1.2V; (gmxZL; No Ext Load); (Note 4) (Note 5) EXTVCC Tied to VOUT; VOUT = 5V VRUN/SS = 0V VRUN/SS = 1.9V VRUN/SS Rising - 0.5 1.0
q q q q q
MIN 0.792 62
TYP 0.800 75 -5 0.1 - 0.1 0.002
MAX 0.808 88 - 50 0.5 - 0.5 0.02 0.88 4
UNITS V mV nA % % %/V V V mmho V/mV A A A V
VREFLNREG VOVL UVLO gm gmOL IQ
Reference Voltage Line Regulation Output Overvoltage Threshold Undervoltage Lockout Transconductance Amplifier gm Transconductance Amplifier Gain Input DC Supply Current Normal Mode Shutdown Soft-Start Charge Current RUN/SS Pin ON Arming
0.84 3
0.86 3.5 3 1.5 470 20 -1.2 1.5
40 1.9
IRUN/SS VRUN/SS
2
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W
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WW
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LTC1709
ELECTRICAL CHARACTERISTICS
SYMBOL VRUN/SSLO ISCL ISDLHO ISENSE DFMAX TG1, 2 tr TG1, 2 tf BG1, 2 tr BG1, 2 tf TG/BG t1D BG/TG t2D tON(MIN) VINTVCC VLDO INT VLDO EXT VEXTVCC VLDOHYS RATTEN ATTENERR RPULLUP VIDTHLOW VIDTHHIGH VIDLEAK fNOM fLOW fHIGH RPLLIN IPLLFLTR PARAMETER RUN/SS Pin Latchoff Arming RUN/SS Discharge Current Shutdown Latch Disable Current Total Sense Pins Source Current Maximum Duty Factor Top Gate Transition Time: Rise Time Fall Time Bottom Gate Transition Time: Rise Time Fall Time Top Gate Off to Bottom Gate On Delay Synchronous Switch-On Delay Time Bottom Gate Off to Top Gate On Delay Top Switch-On Delay Time Minimum On-Time Internal VCC Voltage INTVCC Load Regulation EXTVCC Voltage Drop EXTVCC Switchover Voltage EXTVCC Switchover Hysteresis Resistance Between ATTENIN and ATTENOUT Pins Resistive Divider Worst-Case Error VID0-VID4 Pull-Up Resistance VID0-VID4 Logic Threshold Low VID0-VID4 Logic Threshold High VID0-VID4 Leakage Nominal Frequency Lowest Frequency Highest Frequency PLLIN Input Resistance Phase Detector Output Current Sinking Capability Sourcing Capability Controller 2-Controller 1 Phase Gain Common Mode Rejection Ratio Differential Amp Mode Differential Amp Mode; 0V < VCM < 5V 0.995 46 fPLLIN < fOSC fPLLIN > fOSC VBIAS < VID0-VID4 < 7V VPLLFLTR = 1.2V VPLLFLTR = 0V VPLLFLTR 2.4V 190 120 280 220 140 310 50 - 15 15 180 1 55 1.005 1.6 1 250 160 360 Programmed from 1.3V to 2.05V (VID4 = 0) Programmed from 2.1V to 3.5V (VID4 = 1) (Note 8)
q q
The q denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. VIN = 15V, VRUN/SS = 5V unless otherwise noted.
CONDITIONS VRUN/SS Rising from 3V Soft Short Condition VEAIN = 0.5V; VRUN/SS = 4.5V VEAIN = 0.5V Each Channel: VSENSE1 -, 2 - = VSENSE1+, 2 + = 0V In Dropout (Note 6) CLOAD = 3300pF CLOAD = 3300pF (Note 6) CLOAD = 3300pF CLOAD = 3300pF (Note 6) CLOAD = 3300pF Each Driver (Note 6) CLOAD = 3300pF Each Driver Tested with a Square Wave (Note 7) 6V < VIN < 30V; VEXTVCC = 4V ICC = 0 to 20mA; VEXTVCC = 4V ICC = 20mA; VEXTVCC = 5V ICC = 20mA, EXTVCC Ramping Positive ICC = 20mA, EXTVCC Ramping Negative
q
MIN 0.5
TYP 4.1 2 1.6
MAX 4.5 4 5
UNITS V A A A %
- 85 98
- 60 99.5 30 40 30 20 90 90 180 200 5.2 1.0 240 90 90 90 90
ns ns ns ns ns ns ns V % mV V V k
Internal VCC Regulator 4.8 5.0 0.2 120 4.5 4.7 0.2 20 - 0.25 - 0.35 40 0.4 + 0.25 + 0.25
VID Parameters
% % k V V A kHz kHz kHz k A A Deg V/V dB
Oscillator and Phase-Locked Loop
RRELPHS ADA CMRRDA
Differential Amplifier/Op Amp Gain Block (Note 9)
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LTC1709
ELECTRICAL CHARACTERISTICS
SYMBOL RIN VOS IB AOL VCM CMRROA PSRROA ICL VO(MAX) GBW SR PARAMETER Input Resistance Input Offset Voltage Input Bias Current Open Loop DC Gain Common Mode Input Voltage Range Common Mode Rejection Ratio Power Supply Rejection Ratio Maximum Output Current Maximum Output Voltage Gain-Bandwidth Product Slew Rate
The q denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. VIN = 15V, VRUN/SS = 5V unless otherwise noted.
CONDITIONS Differential Amp Mode; Measured at VOS + Input Op Amp Mode; VCM = 2.5V; VDIFFOUT = 5V; IDIFFOUT = 1mA Op Amp Mode Op Amp Mode; 0.7V VDIFFOUT < 10V Op Amp Mode Op Amp Mode; 0V < VCM < 3V Op Amp Mode; 6V < VIN < 30V Op Amp Mode; VDIFFOUT = 0V Op Amp Mode; IDIFFOUT = 1mA Op Amp Mode; IDIFFOUT = 1mA Op Amp Mode; RL = 2k 0 70 70 10 10 90 90 35 11 2 5 30 5000 3 MIN TYP 80 6 200 MAX UNITS k mV nA V/mV V dB dB mA V MHz V/s
Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Note 2: The LTC1709EG is guaranteed to meet performance specifications from 0C to 70C. Specifications over the - 40C to 85C operating temperature range are assured by design, characterization and correlation with statistical process controls. Note 3: TJ is calculated from the ambient temperature TA and power dissipation PD according to the following formulas: LTC1709EG: TJ = TA + (PD * 85C/W) Note 4: The LTC1709 is tested in a feedback loop that servos VITH to a specified voltage and measures the resultant VEAIN. Note 5: Dynamic supply current is higher due to the gate charge being delivered at the switching frequency. See Applications Information.
Note 6: Rise and fall times are measured using 10% and 90% levels. Delay times are measured using 50% levels. Note 7: The minimum on-time condition corresponds to the on inductor peak-to-peak ripple current 40% IMAX (see Minimum On-Time Considerations in the Applications Information section). Note 8: Each built-in pull-up resistor attached to the VID inputs also has a series diode to allow input voltages higher than the VIDVCC supply without damage or clamping (see the Applications Information section). Note 9: When the AMPMD pin is high, the IC pins are connected directly to the internal op amp inputs. When the AMPMD pin is low, internal MOSFET switches connect four 40k resistors around the op amp to create a standard unity-gain differential amp.
TYPICAL PERFOR A CE CHARACTERISTICS
Efficiency vs Output Current (Figure 12)
100 100 VOUT = 2V VIN = 12V f = 200kHz
EFFICIENCY (%)
80 VIN = 5V
EFFICIENCY (%)
60
EFFICIENCY (%)
VIN = 8V VIN = 12V VIN = 20V
40
20
VOUT = 2V VEXTVCC = 0V f = 200kHz 0.1 1 10 OUTPUT CURRENT (A) 100
1709 G01
0
4
UW
Efficiency vs Output Current (Figure 12)
100
Efficiency vs Input Voltage (Figure 12)
VOUT = 3.3V VEXTVCC = 5V IOUT = 20A 90
80
60
VEXTVCC = 5V VEXTVCC = 0V
40
80
20
INTERNAL LDO VS EXTERNALLY APPLIED 5V OVERALL EFFICIENCY (FIGURE 12) 70 1 10 OUTPUT CURRENT (A) 100
1709 G02
0 0.1
5
10 VIN (V)
15
20
1709 G03
LTC1709 TYPICAL PERFOR A CE CHARACTERISTICS
Supply Current vs Input Voltage and Mode
1000 250
INTVCC AND EXTVCC SWITCH VOLTAGE (V)
EXTVCC VOLTAGE DROP (mV)
800
SUPPLY CURRENT (A)
600 ON 400
200 SHUTDOWN 0 0 5 20 15 10 25 INPUT VOLTAGE (V) 30 35
Internal 5V LDO Line Reg
5.1 5.0
ILOAD = 1mA
INTVCC VOLTAGE (V)
4.9
VSENSE (mV)
4.8 4.7 4.6 4.5 4.4 0 5 20 15 25 10 INPUT VOLTAGE (V) 30 35
1709 G07
VSENSE (mV)
Maximum Current Sense Threshold vs VRUN/SS (Soft-Start)
80 VSENSE(CM) = 1.6V
80
60
VSENSE (mV)
VSENSE (mV)
72
VSENSE (mV)
40
20
64
0 0 1 2 3 VRUN/SS (V)
1709 G10
4
UW
1709 G04
EXTVCC Voltage Drop
5.05 5.00 4.95 4.90 4.85 4.80 4.75
INTVCC and EXTVCC Switch Voltage vs Temperature
INTVCC VOLTAGE
200
150
100
50
EXTVCC SWITCHOVER THRESHOLD
0
0
10
30 20 CURRENT (mA)
40
50
1709 G05
4.70 - 50 - 25
50 25 75 0 TEMPERATURE (C)
100
125
1709 G06
Maximum Current Sense Threshold vs Duty Factor
75
80 70 60
Maximum Current Sense Threshold vs Percent of Nominal Output Voltage (Foldback)
50
50 40 30 20 10
25
0 0 20 40 60 DUTY FACTOR (%) 80 100
1709 G08
0
50 100 0 25 75 PERCENT ON NOMINAL OUTPUT VOLTAGE (%)
1709 G09
Maximum Current Sense Threshold vs Sense Common Mode Voltage
90 80 76 70 60 50 40 30 20 10 0 -10 -20 60 -30
Current Sense Threshold vs ITH Voltage
68
5
6
0
1 3 4 2 COMMON MODE VOLTAGE (V)
5
1709 G11
0
0.5
1
1.5 VITH (V)
2
2.5
1709 G12
5
LTC1709 TYPICAL PERFOR A CE CHARACTERISTICS
Load Regulation
0.0 FCB = 0V VIN = 15V FIGURE 1
2.5
NORMALIZED VOUT (%)
-0.1
-0.2
VITH (V)
1.5
ISENSE (A)
-0.3
0.5
-0.4
0
1
3 2 LOAD CURRENT (A)
Maximum Current Sense Threshold vs Temperature
80 1.8 1.6 78
RUN/SS CURRENT (A)
VSENSE (mV)
76
74
72
70 -50
-25
50 25 0 75 TEMPERATURE (C)
Load Step Response Using Active Voltage Positioning (Figure 12)
35
CURRENT SENSE INPUT CURRENT (A)
VOUT 50mV/DIV
33
EXTVCC SWITCH RESISTANCE ()
20A IOUT 10A/DIV
0A
20s/DIV
6
UW
4 5
1709 G13
VITH vs VRUN/SS
VOSENSE = 0.7V
SENSE Pins Total Source Current
100
2.0
50
0
1.0
-50
0
0
1
2
3 VRUN/SS (V)
4
5
6
1709 G14
-100
0
2
4
6
1709 G15
VSENSE COMMON MODE VOLTAGE (V)
RUN/SS Current vs Temperature
VITH 1V/DIV
Soft-Start Up (Figure 12)
1.4 1.2 1.0 0.8 0.6 0.4 0.2
VOUT 2V/DIV VRUNSS 2V/DIV
100ms/DIV
1629 G19
100
125
0 -50
-25
0 25 50 75 TEMPERATURE (C)
100
125
1709 G17
1709 G18
Current Sense Pin Input Current vs Temperature
10 EXTVCC = 5V 8
EXTVCC Switch Resistance vs Temperature
31
6
29
4
27
2
1709 G20
25 -50 -25
50 25 0 75 TEMPERATURE (C)
100
125
0 -50 -25
50 25 0 75 TEMPERATURE (C)
100
125
1709 G21
1709 G22
LTC1709 TYPICAL PERFOR A CE CHARACTERISTICS
Oscillator Frequency vs Temperature
350 VFREQSET = 5V
UNDERVOLTAGE LOCKOUT (V)
300
3.45 3.40 3.35 3.30 3.25 3.20 -50 -25
SHUTDOWN LATCH THRESHOLDS (V)
FREQUENCY (kHz)
250 VFREQSET = OPEN 200 150 100 50 0 - 50 - 25 VFREQSET = 0V
50 25 75 0 TEMPERATURE (C)
PI FU CTIO S
RUN/SS (Pin 1): Combination of Soft-Start, Run Control Input and Short-Circuit Detection Timer. A capacitor to ground at this pin sets the ramp time to full current output. Forcing this pin below 0.8V causes the IC to shut down all internal circuitry. All functions are disabled in shutdown. SENSE 1+, SENSE 2+ (Pins 2,14): The (+) Input to Each Differential Current Comparator. The ITH pin voltage and built-in offsets between SENSE- and SENSE+ pins in conjunction with RSENSE set the current trip threshold. SENSE 1-, SENSE 2- (Pins 3, 13): The (-) Input to the Differential Current Comparators. EAIN (Pin 4): Input to the Error Amplifier that compares the feedback voltage to the internal 0.8V reference voltage. This pin is normally connected to a resistive divider from the output of the differential amplifier (DIFFOUT). PLLFLTR (Pin 5): The Phase-Locked Loop's Low Pass Filter is tied to this pin. Alternatively, this pin can be driven with an AC or DC voltage source to vary the frequency of the internal oscillator. PLLIN (Pin 6): External Synchronization Input to Phase Detector. This pin is internally terminated to SGND with 50k. The phase-locked loop will force the rising top gate signal of controller 1 to be synchronized with the rising edge of the PLLIN signal. NC (Pins 7, 36): Do not connect. ITH (Pin 8): Error Amplifier Output and Switching Regulator Compensation Point. Both current comparator's thresholds increase with this control voltage. The normal voltage range of this pin is from 0V to 2.4V SGND (Pin 9): Signal Ground, common to both controllers. Route separately to the PGND pin. VDIFFOUT (Pin 10): Output of a Differential Amplifier that provides true remote output voltage sensing. This pin normally drives an external resistive divider that sets the output voltage. VOS-, VOS+ (Pins 11, 12): Inputs to an Operational Amplifier. Internal precision resistors capable of being electronically switched in or out can configure it as a differential amplifier or an uncommitted Op Amp. ATTENOUT (Pin 15): Voltage Feedback Signal Resistively Divided According to the VID Programming Code. ATTENIN (Pin 16): The Input to the VID Controlled Resistive Divider. VID0-VID4 (Pins 17,18, 19, 20, 21): VID Control Logic Input Pins. VBIAS (Pin 22): Supply Pin for the VID Control Circuit.
UW
100
Undervoltage Lockout vs Temperature
3.50 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5
VRUN/SS Shutdown Latch Thresholds vs Temperature
LATCH ARMING
LATCHOFF THRESHOLD
125
50 25 75 0 TEMPERATURE (C)
100
125
0 -50
-25
0 25 50 75 TEMPERATURE (C)
100
125
1709 G23
1709 G24
1709 G25
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LTC1709
PI FU CTIO S
AMPMD (Pin 23): This Logic Input pin controls the connections of internal precision resistors that configure the operational amplifier as a unity-gain differential amplifier. TG2, TG1 (Pins 24, 35): High Current Gate Drives for Top N-Channel MOSFETS. These are the outputs of floating drivers with a voltage swing equal to INTVCC superimposed on the switch node voltage SW. SW2, SW1 (Pins 25, 34): Switch Node Connections to Inductors. Voltage swing at these pins is from a Schottky diode (external) voltage drop below ground to VIN. BOOST 2, BOOST 1 (Pins 26, 33): Bootstrapped Supplies to the Topside Floating Drivers. External capacitors are connected between the Boost and Switch pins, and Schottky diodes are connected between the Boost and INTVCC pins. BG2, BG1 (Pins 27, 31): High Current Gate Drives for Bottom N-Channel MOSFETS. Voltage swing at these pins is from ground to INTVCC. PGND (Pin 28): Driver Power Ground, connect to sources of bottom N-channel MOSFETS and the (-) terminals of CIN. INTVCC (Pin 29): Output of the Internal 5V Linear Low Dropout Regulator and the EXTVCC Switch. The driver and control circuits are powered from this voltage source. Decouple to power ground with a 1F ceramic capacitor placed directly adjacent to the IC and minimum of 4.7F additional tantalum or other low ESR capacitor. EXTVCC (Pin 30): External Power Input to an Internal Switch . This switch closes and supplies INTVCC, bypassing the internal low dropout regulator whenever EXTVCC is higher than 4.7V. See EXTVCC Connection in the Applications Information section. Do not exceed 7V on this pin and ensure VEXTVCC VIN. VIN (Pin 32): Main Supply Pin. Should be closely decoupled to the IC's signal ground pin.
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LTC1709
FU CTIO AL DIAGRA
PLLIN FIN 50k PLLFLTR RLP CLP CLK1 OSCILLATOR CLK2 S TO SECOND CHANNEL R Q Q DROP OUT DET TOP BOT FORCE BOT SWITCH LOGIC BOT INTVCC BG PGND* VOS - SHDN VOS + A1 - + I1 - + 4(VFB) AMPMD 0V POSITION DIFFOUT SLOPE COMP 45k 45k 2.4V VIN VIN 4.7V EXTVCC + - 5V LDO REG 0.8V VREF VFB 0.80V EAIN INTVCC SW TG CB PHASE DET DUPLICATE FOR SECOND CHANNEL BOOST INTVCC DB VIN
VOUT
- EA + OV + VIN 1.2A
SHDN RST 4(VFB)
-
0.86V
ITH
CC
+
5V
INTVCC
SGND
INTERNAL SUPPLY
6V
RUN SOFTSTART RUN/SS
RC
ATTENIN R2 20k 5-BIT VID DECODER ATTENOUT R1 R1 VARIABLE TYPICAL ALL VID PINS 40k
CSS
VID0
VID1
VID2
VID3
VID4
VBIAS
1709 FBD
+
W
+
CIN
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-
+
L
+ 30k SENSE - 30k SENSE
RSENSE
COUT
9
LTC1709
OPERATIO
Main Control Loop The LTC1709 uses a constant frequency, current mode step-down architecture with inherent current sharing. During normal operation, the top MOSFET is turned on each cycle when the oscillator sets the RS latch, and turned off when the main current comparator, I1, resets the RS latch. The peak inductor current at which I1 resets the RS latch is controlled by the voltage on the ITH pin, which is the output of the error amplifier EA. The differential amplifier, A1, produces a signal equal to the differential voltage sensed across the output capacitor but re-references it to the internal signal ground (SGND) reference. The EAIN pin receives a portion of this voltage feedback signal at the DIFFOUT as determined by VID logic input pins (VID0 to VID4) and is compared to the internal reference voltage by the EA. When the load current increases, it causes a slight decrease in the EAIN pin voltage relative to the 0.8V reference, which in turn causes the ITH voltage to increase until the average inductor current matches the new load current. After the top MOSFET has turned off, the bottom MOSFET is turned on for the rest of the period. The top MOSFET drivers are biased from floating bootstrap capacitor CB, which normally is recharged during each off cycle through an external Schottky diode. When VIN decreases to a voltage close to VOUT, however, the loop may enter dropout and attempt to turn on the top MOSFET continuously. A dropout detector detects this condition and forces the top MOSFET to turn off for about 400ns every 10th cycle to recharge the bootstrap capacitor, CB. The main control loop is shut down by pulling Pin 1 (RUN/ SS) low. Releasing RUN/SS allows an internal 1.2A current source to charge soft-start capacitor CSS. When CSS reaches 1.5V, the main control loop is enabled with the ITH voltage clamped at approximately 30% of its maximum value. As CSS continues to charge, ITH is gradually released allowing normal operation to resume. When the RUN/SS pin is low, all LTC1709 functions are shut down. If VOUT has not reached 70% of its nominal value when CSS has charged to 4.1V, an overcurrent latchoff can be invoked as described in the Applications Information section.
10
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(Refer to Functional Diagram)
Low Current Operation The LTC1709 operates in a continuous, PWM control mode. The resulting operation at low output currents optimizes transient response at the expense of substantial negative inductor current during the latter part of the period. The level of ripple current is determined by the inductor value, input voltage, output voltage, and frequency of operation. Frequency Synchronization The phase-locked loop allows the internal oscillator to be synchronized to an external source via the PLLIN pin. The output of the phase detector at the PLLFLTR pin is also the DC frequency control input of the oscillator that operates over a 140kHz to 310kHz range corresponding to a DC voltage input from 0V to 2.4V. When locked, the PLL aligns the turn on of the top MOSFET to the rising edge of the synchronizing signal. When PLLIN is left open, the PLLFLTR pin goes low, forcing the oscillator to minimum frequency. Input capacitance ESR requirements and efficiency losses are substantially reduced because the peak current drawn from the input capacitor is effectively divided by two and power loss is proportional to the RMS current squared. A two stage, single output voltage implementation can reduce input path power loss by 75% and radically reduce the required RMS current rating of the input capacitor(s). INTVCC/EXTVCC Power Power for the top and bottom MOSFET drivers and most of the IC circuitry is derived from INTVCC. When the EXTVCC pin is left open, an internal 5V low dropout regulator supplies INTVCC power. If the EXTVCC pin is taken above 4.7V, the 5V regulator is turned off and an internal switch is turned on connecting EXTVCC to INTVCC. This allows the INTVCC power to be derived from a high efficiency external source such as the output of the regulator itself or a secondary winding, as described in the Applications Information section. An external Schottky diode can be used to minimize the voltage drop from EXTVCC to INTVCC in applications requiring greater than the specified INTVCC current. Voltages up to 7V can be applied to EXTVCC for additional gate drive capability.
LTC1709
OPERATIO
Differential Amplifier This amplifier provides true differential output voltage sensing. Sensing both VOUT + and VOUT - benefits regulation in high current applications and/or applications having electrical interconnection losses. The AMPMD pin allows selection of internal, precision feedback resistors for high common mode rejection differencing applications, or direct access to the actual amplifier inputs without these internal feedback resistors for other applications. The AMPMD pin is grounded to connect the internal precision resistors in a unity-gain differencing application, or tied to the INTVCC pin to bypass the internal resistors and make the amplifier inputs directly available. The amplifier is a unity-gain stable, 2MHz gain-bandwidth, >120dB open-loop gain design. The amplifier has an output slew rate of 5V/s and is capable of driving capacitive loads with an output RMS current typically up to 35mA. The amplifier is not capable of sinking current and therefore must be resistively loaded to do so.
APPLICATIO S I FOR ATIO
The basic LTC1709 application circuit is shown in Figure 1 on the first page. External component selection begins with the selection of the inductor(s) based on ripple current requirements and continues with the RSENSE1, 2 resistor selection using the calculated peak inductor current and/or maximum current limit. Next, the power MOSFETs and D1 and D2 are selected. The operating frequency and the inductor are chosen based mainly on the amount of ripple current. Finally, CIN is selected for its ability to handle the input ripple current (that PolyPhaseTM operation minimizes) and COUT is chosen with low enough ESR to meet the output ripple voltage and load step specifications (also minimized with PolyPhase). Current mode architecture provides inherent current sharing between output stages. The circuit shown in Figure 1 can be configured for operation up to an input voltage of 28V (limited by the external MOSFETs). RSENSE Selection For Output Current RSENSE1, 2 are chosen based on the required peak output
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(Refer to Functional Diagram)
Short-Circuit Detection The RUN/SS capacitor is used initially to limit the inrush current from the input power source. Once the controllers have been given time, as determined by the capacitor on the RUN/SS pin, to charge up the output capacitors and provide full-load current, the RUN/SS capacitor is then used as a short-circuit timeout circuit. If the output voltage falls to less than 70% of its nominal output voltage the RUN/SS capacitor begins discharging assuming that the output is in a severe overcurrent and/or short-circuit condition. If the condition lasts for a long enough period as determined by the size of the RUN/SS capacitor, the controller will be shut down until the RUN/SS pin voltage is recycled. This built-in latchoff can be overidden by providing a current >5A at a compliance of 5V to the RUN/SS pin. This current shortens the soft-start period but also prevents net discharge of the RUN/SS capacitor during a severe overcurrent and/or short-circuit condition. Foldback current limiting is activated when the output voltage falls below 70% of its nominal level whether or not the short-circuit latchoff circuit is enabled.
current. The LTC1709 current comparator has a maximum threshold of 75mV/RSENSE and an input common mode range of SGND to 1.1( INTVCC). The current comparator threshold sets the peak inductor current, yielding a maximum average output current IMAX equal to the peak value less half the peak-to-peak ripple current, IL. Allowing a margin for variations in the LTC1709 and external component values yields: RSENSE = 2(50mV/IMAX) Operating Frequency The LTC1709 uses a constant frequency, phase-lockable architecture with the frequency determined by an internal capacitor. This capacitor is charged by a fixed current plus an additional current which is proportional to the voltage applied to the PLLFLTR pin. Refer to Phase-Locked Loop and Frequency Synchronization in the Applications Information section for additional information.
PolyPhase is a registered trademark of Linear Technology Corporation.
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A graph for the voltage applied to the PLLFLTR pin vs frequency is given in Figure 2. As the operating frequency is increased the gate charge losses will be higher, reducing efficiency (see Efficiency Considerations). The maximum switching frequency is approximately 310kHz.
2.5
PLLFLTR PIN VOLTAGE (V)
2.0
1.5
1.0
0.5
0 120
170 220 270 OPERATING FREQUENCY (kHz)
320
1709 F02
Figure 2. Operating Frequency vs VPLLFLTR
Inductor Value Calculation and Output Ripple Current The operating frequency and inductor selection are interrelated in that higher operating frequencies allow the use of smaller inductor and capacitor values. So why would anyone ever choose to operate at lower frequencies with larger components? The answer is efficiency. A higher frequency generally results in lower efficiency because MOSFET gate charge and transition losses increase directly with frequency. In addition to this basic tradeoff, the effect of inductor value on ripple current and low current operation must also be considered. The PolyPhase approach reduces both input and output ripple currents while optimizing individual output stages to run at a lower fundamental frequency, enhancing efficiency. The inductor value has a direct effect on ripple current. The inductor ripple current IL per individual section, N, decreases with higher inductance or frequency and increases with higher VIN or VOUT:
IL = VOUT VOUT 1- fL VIN
IO(P-P)
VO/fL
where f is the individual output stage operating frequency.
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In a 2-phase converter, the net ripple current seen by the output capacitor is much smaller than the individual inductor ripple currents due to ripple cancellation. The details on how to calculate the net output ripple current can be found in Application Note 77. Figure 3 shows the net ripple current seen by the output capacitors for the 1- and 2- phase configurations. The output ripple current is plotted for a fixed output voltage as the duty factor is varied between 10% and 90% on the x-axis. The output ripple current is normalized against the inductor ripple current at zero duty factor. The graph can be used in place of tedious calculations, simplifying the design process. Accepting larger values of IL allows the use of low inductances, but can result in higher output voltage ripple. A reasonable starting point for setting ripple current is IL = 0.4(IOUT)/2, where IOUT is the total load current. Remember, the maximum IL occurs at the maximum input voltage. The individual inductor ripple currents are determined by the inductor, input and output voltages.
1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 DUTY FACTOR (VOUT/VIN) 0.8 0.9 1-PHASE 2-PHASE
1709 F03
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Figure 3. Normalized Output Ripple Current vs Duty Factor [IRMS 0.3 (IO(P-P))]
Inductor Core Selection Once the values for L1 and L2 are known, the type of inductor must be selected. High efficiency converters generally cannot afford the core loss found in low cost powdered iron cores, forcing the use of more expensive ferrite, molypermalloy, or Kool M(R) cores. Actual core loss is independent of core size for a fixed inductor value,
Kool M is a registered trademark of Magnetics, Inc.
LTC1709
APPLICATIO S I FOR ATIO
but it is very dependent on inductance selected. As inductance increases, core losses go down. Unfortunately, increased inductance requires more turns of wire and therefore copper losses will increase. Ferrite designs have very low core loss and are preferred at high switching frequencies, so design goals can concentrate on copper loss and preventing saturation. Ferrite core material saturates "hard," which means that inductance collapses abruptly when the peak design current is exceeded. This results in an abrupt increase in inductor ripple current and consequent output voltage ripple. Do not allow the core to saturate! Molypermalloy (from Magnetics, Inc.) is a very good, low loss core material for toroids, but it is more expensive than ferrite. A reasonable compromise from the same manufacturer is Kool M. Toroids are very space efficient, especially when you can use several layers of wire. Because they lack a bobbin, mounting is more difficult. However, designs for surface mount are available which do not increase the height significantly. Power MOSFET, D1 and D2 Selection Two external power MOSFETs must be selected for each output stage for the LTC1709: One N-channel MOSFET for the top (main) switch, and one N-channel MOSFET for the bottom (synchronous) switch. The peak-to-peak drive levels are set by the INTVCC voltage. This voltage is typically 5V during start-up (see EXTVCC Pin Connection). Consequently, logic-level threshold MOSFETs must be used in most applications. The only exception is if low input voltage is expected (VIN < 5V); then, sublogic-level threshold MOSFETs (VGS(TH) < 1V) should be used. Pay close attention to the BVDSS specification for the MOSFETs as well; most of the logic-level MOSFETs are limited to 30V or less. Selection criteria for the power MOSFETs include the "ON" resistance RDS(ON), reverse transfer capacitance CRSS, input voltage, and maximum output current. When the LTC1709 is operating in continuous mode the duty factors for the top and bottom MOSFETs of each output stage are given by:
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Main Switch Duty Cycle = VOUT VIN
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V -V Synchronous Switch Duty Cycle = IN OUT VIN
The MOSFET power dissipations at maximum output current are given by: I V PMAIN = OUT MAX 1 + RDS(ON) + VIN 2 2 I k VIN MAX CRSS f 2
2
()
()
(
)( )
I V -V PSYNC = IN OUT MAX 1 + RDS(ON) VIN 2
2
()
where is the temperature dependency of RDS(ON) and k is a constant inversely related to the gate drive current. Both MOSFETs have I2R losses but the topside N-channel equation includes an additional term for transition losses, which peak at the highest input voltage. For VIN < 20V the high current efficiency generally improves with larger MOSFETs, while for VIN > 20V the transition losses rapidly increase to the point that the use of a higher RDS(ON) device with lower CRSS actual provides higher efficiency. The synchronous MOSFET losses are greatest at high input voltage when the top switch duty factor is low or during a short-circuit when the synchronous switch is on close to 100% of the period. The term (1 + ) is generally given for a MOSFET in the form of a normalized RDS(ON) vs. Temperature curve, but = 0.005/C can be used as an approximation for low voltage MOSFETs. CRSS is usually specified in the MOSFET characteristics. The constant k = 1.7 can be used to estimate the contributions of the two terms in the main switch dissipation equation. The Schottky diodes, D1 and D2 shown in Figure 1 conduct during the dead-time between the conduction of the two large power MOSFETs. This helps prevent the body diode
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of the bottom MOSFET from turning on, storing charge during the dead-time, and requiring a reverse recovery period which would reduce efficiency. A 1A to 3A Schottky (depending on output current) diode is generally a good compromise for both regions of operation due to the relatively small average current. Larger diodes result in additional transition losses due to their larger junction capacitance. CIN and COUT Selection In continuous mode, the source current of each top N-channel MOSFET is a square wave of duty cycle VOUT/ VIN. A low ESR input capacitor sized for the maximum RMS current must be used. The details of a closed form equation can be found in Application Note 77. Figure 4 shows the input capacitor ripple current for a 2-phase configuration with the output voltage fixed and input voltage varied. The input ripple current is normalized against the DC output current. The graph can be used in place of tedious calculations. The minimum input ripple current can be achieved when the input voltage is twice the output voltage In the graph of Figure 4, the 2-phase local maximum input RMS capacitor currents are reached when:
VOUT 2k - 1 = VIN 4
where k = 1, 2.
0.6 0.5
DC LOAD CURRENT
RMS INPUT RIPPLE CURRNET
0.4 0.3 0.2 0.1 0
1-PHASE 2-PHASE
0.1
0.2
0.3 0.4 0.5 0.6 0.7 DUTY FACTOR (VOUT/VIN)
0.8
0.9
1709 F04
Figure 4. Normalized RMS Input Ripple Current vs Duty Factor for 1 and 2 Output Stages
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These worst-case conditions are commonly used for design because even significant deviations do not offer much relief. Note that capacitor manufacturer's ripple current ratings are often based on only 2000 hours of life. This makes it advisable to further derate the capacitor, or to choose a capacitor rated at a higher temperature than required. Several capacitors may also be paralleled to meet size or height requirements in the design. Always consult the capacitor manufacturer if there is any question. It is important to note that the efficiency loss is proportional to the input RMS current squared and therefore a 2-phase implementation results in 75% less power loss when compared to a single phase design. Battery/input protection fuse resistance (if used), PC board trace and connector resistance losses are also reduced by the reduction of the input ripple current in a 2-phase system. The required amount of input capacitance is further reduced by the factor, 2, due to the effective increase in the frequency of the current pulses. The selection of COUT is driven by the required effective series resistance (ESR). Typically once the ESR requirement has been met, the RMS current rating generally far exceeds the IRIPPLE(P-P) requirements. The steady state output ripple (VOUT) is determined by:
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1 VOUT IRIPPLE ESR + 16 fCOUT
Where f = operating frequency of each stage, COUT = output capacitance and IRIPPLE = combined inductor ripple currents. The output ripple varies with input voltage since IL is a function of input voltage. The output ripple will be less than 50mV at max VIN with IL = 0.4IOUT(MAX)/2 assuming: COUT required ESR < 4(RSENSE) and COUT > 1/(16f)(RSENSE) The emergence of very low ESR capacitors in small, surface mount packages makes very physically small implementations possible. The ability to externally compensate the switching regulator loop using the ITH pin(OPTILOOP compensation) allows a much wider selection of
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APPLICATIO S I FOR ATIO
output capacitor types. OPTI-LOOP compensation effectively removes constraints on output capacitor ESR. The impedance characteristics of each capacitor type are significantly different than an ideal capacitor and therefore require accurate modeling or bench evaluation during design. Manufacturers such as Nichicon, United Chemicon and Sanyo should be considered for high performance throughhole capacitors. The OS-CON semiconductor dielectric capacitor available from Sanyo and the Panasonic SP surface mount types have the lowest (ESR)(size) product of any aluminum electrolytic at a somewhat higher price. An additional ceramic capacitor in parallel with OS-CON type capacitors is recommended to reduce the inductance effects. In surface mount applications, multiple capacitors may have to be paralleled to meet the ESR or RMS current handling requirements of the application. Aluminum electrolytic and dry tantalum capacitors are both available in surface mount configurations. New special polymer surface mount capacitors offer very low ESR also but have much lower capacitive density per unit volume. In the case of tantalum, it is critical that the capacitors are surge tested for use in switching power supplies. Several excellent choices are the AVX TPS, AVX TPSV or the KEMET T510 series of surface mount tantalums, available in case heights ranging from 2mm to 4mm. Other capacitor types include Sanyo OS-CON, Nichicon PL series and Sprague 595D series. Consult the manufacturer for other specific recommendations. A combination of capacitors will often result in maximizing performance and minimizing overall cost and size. INTVCC Regulator An internal P-channel low dropout regulator produces 5V at the INTVCC pin from the VIN supply pin. The INTVCC regulator powers the drivers and internal circuitry of the LTC1709. The INTVCC pin regulator can supply up to 50mA peak and must be bypassed to power ground with a minimum of 4.7F tantalum or electrolytic capacitor. An additional 1F ceramic capacitor placed very close to the IC is recommended due to the extremely high instantaneous currents required by the MOSFET gate drivers.
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High input voltage applications in which large MOSFETs are being driven at high frequencies may cause the maximum junction temperature rating for the LTC1709 to be exceeded. The supply current is dominated by the gate charge supply current, in addition to the current drawn from the differential amplifier output. The gate charge is dependent on operating frequency as discussed in the Efficiency Considerations section. The supply current can either be supplied by the internal 5V regulator or via the EXTVCC pin. When the voltage applied to the EXTVCC pin is less than 4.7V, all of the INTVCC load current is supplied by the internal 5V linear regulator. Power dissipation for the IC is higher in this case by (IIN)(VIN - INTVCC) and efficiency is lowered. The junction temperature can be estimated by using the equations given in Note 1 of the Electrical Characteristics. For example, the LTC1709 VIN current is limited to less than 24mA from a 24V supply: TJ = 70C + (24mA)(24V)(85C/W) = 119C Use of the EXTVCC pin reduces the junction temperature to: TJ = 70C + (24mA)(5V)(85C/W) = 80.2C The input supply current should be measured while the controller is operating in continuous mode at maximum VIN and the power dissipation calculated in order to prevent the maximum junction temperature from being exceeded. EXTVCC Connection The LTC1709 contains an internal P-channel MOSFET switch connected between the EXTVCC and INTVCC pins. When the voltage applied to EXTVCC rises above 4.7V, the internal regulator is turned off and an internal switch closes, connecting the EXTVCC pin to the INTVCC pin thereby supplying internal and MOSFET gate driving power to the IC. The switch remains closed as long as the voltage applied to EXTVCC remains above 4.5V. This allows the MOSFET driver and control power to be derived from the output during normal operation (4.7V < VEXTVCC < 7V) and from the internal regulator when the output is out of regulation (start-up, short-circuit). Do not apply greater than 7V to the EXTVCC pin and ensure that EXTVCC < VIN + 0.3V when using the application circuits shown. If an
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external voltage source is applied to the EXTVCC pin when the VIN supply is not present, a diode can be placed in series with the LTC1709's VIN pin and a Schottky diode between the EXTVCC and the VIN pin, to prevent current from backfeeding VIN. Significant efficiency gains can be realized by powering INTVCC from the output, since the VIN current resulting from the driver and control currents will be scaled by the ratio: (Duty Factor)/(Efficiency). For 5V regulators this means connecting the EXTVCC pin directly to VOUT. However, for 3.3V and other lower voltage regulators, additional circuitry is required to derive INTVCC power from the output. The following list summarizes the four possible connections for EXTVCC: 1. EXTVCC left open (or grounded). This will cause INTVCC to be powered from the internal 5V regulator resulting in a significant efficiency penalty at high input voltages. 2. EXTVCC connected directly to VOUT. This is the normal connection for a 5V regulator and provides the highest efficiency. 3. EXTVCC connected to an external supply. If an external supply is available in the 5V to 7V range, it may be used to power EXTVCC providing it is compatible with the MOSFET gate drive requirements. 4. EXTVCC connected to an output-derived boost network. For 3.3V and other low voltage regulators, efficiency gains can still be realized by connecting EXTVCC to an outputderived voltage which has been boosted to greater than
OPTIONAL EXTVCC CONNECTION 5V < VSEC < 7V + CIN LTC1709 VIN TG1 EXTVCC SW1 N-CH RSENSE T1 VOUT VIN
1N4148
VSEC
+
1F
+
BG1 N-CH PGND
1709 F05a
Figure 5a. Secondary Output Loop with EXTVCC Connection
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4.7V but less than 7V. This can be done with either the inductive boost winding as shown in Figure 5a or the capacitive charge pump shown in Figure 5b. The charge pump has the advantage of simple magnetics. Topside MOSFET Driver Supply (CB,DB) (Refer to Functional Diagram) External bootstrap capacitors CB1 and CB2 connected to the BOOST 1 and BOOST 2 pins supply the gate drive voltages for the topside MOSFETs. Capacitor CB in the Functional Diagram is charged though diode DB from INTVCC when the SW pin is low. When the topside MOSFET turns on, the driver places the CB voltage across the gatesource of the desired MOSFET. This enhances the MOSFET and turns on the topside switch. The switch node voltage, SW, rises to VIN and the BOOST pin rises to VIN + VINTVCC. The value of the boost capacitor CB needs to be 30 to 100 times that of the total input capacitance of the topside MOSFET(s). The reverse breakdown of DB must be greater than VIN(MAX). The final arbiter when defining the best gate drive amplitude level will be the input supply current. If a change is made that decreases input current, the efficiency has improved. If the input current does not change then the efficiency has not changed either. Output Voltage The LTC1709 has a true remote voltage sense capablity. The sensing connections should be returned from the load back to the differential amplifier's inputs through a com+
CIN VIN TG1 LTC1709 EXTVCC SW1 L1 N-CH VN2222LL RSENSE VOUT BAT85 BAT85 0.22F BAT85 VIN
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+
COUT
BG1 N-CH PGND
COUT
1709 F05b
Figure 5b. Capacitive Charge Pump for EXTVCC
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mon, tightly coupled pair of PC traces. The differential amplifier corrects for DC drops in both the power and ground paths. The differential amplifier output signal is divided down and compared with the internal precision 0.8V voltage reference by the error amplifier. The differential amplifier can be used in either of two configurations according to the voltage applied to the AMPMD pin. The first configuration with the connections illustrated in the Functional Diagram, utilizes a set of internal, precision resistors to enable precision instrumentation-type measurement of the output voltage. This configuration is activated when the AMPMD pin is tied to ground. When the AMPMD pin is tied to INTVCC, the resistors are disconnected and the amplifier inputs are made directly available. It can be used for general uses if the amplifier is not required for true remote sensing. The amplifier has a 0V to 3V common mode input range limitation due to the internal switching of its inputs. The output uses an NPN emitter follower without any internal pull-down current. A DC resistive load to ground is required in order to sink current. The output will swing from 0V to 10V (VIN VDIFFOUT + 2V). Output Voltage Programming The output voltage is digitally set to levels between 1.3V and 3.5V using the voltage identification (VID) logic inputs VID0 to VID4. The internal 5-bit DAC configured as a precision resistive voltage divider sets the output voltage in 100mV or 50mV increments according to Table 1. The VID codes are engineered to be compatible with Intel Pentium(R) II and Pentium III processor specifications for output voltages from 1.3V to 3.5V. The LSB (VID0) represents 50mV or 100mV increments depending on the MSB. The MSB is VID4. Between the ATTENOUT pin and ground is a variable resistor, R1, whose value is controlled by the five VID input pins (VID0 to VID4). Another resistor, R2, between the ATTENIN and the ATTENOUT pins completes the resistive divider. The output voltage is thus set by the ratio of (R1 + R2) to R1.
Pentium is a registered trademark of Intel Corporation.
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Table 1. VID Output Voltage Programming
VID4 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VID3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 VID2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 VID1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 VID0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 VOUT (V) 3.50V 3.40V 3.30V 3.20V 3.10V 3.00V 2.90V 2.80V 2.70V 2.60V 2.50V 2.40V 2.30V 2.20V 2.10V * 2.05V 2.00V 1.95V 1.90V 1.85V 1.80V 1.75V 1.70V 1.65V 1.60V 1.55V 1.50V 1.45V 1.40V 1.35V 1.30V * Represents codes without a defined output voltage as specified in Intel specifications. The LTC1709 interprets these codes as a valid input and produces an output voltage as follows: (11111) = 2V
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Each VID digital input is pulled up by a 40k resistor in series with a diode from VBIAS. Therefore, it must be grounded to get a digital low input, and can be either
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floated or connected to VBIAS to get a digital high input. The series diode is used to prevent the digital inputs from being damaged or clamped if they are driven higher than VBIAS. The digital inputs accept CMOS voltage levels. VBIAS is the supply voltage for the VID section. It is normally connected to INTVCC but can be driven from other sources. If it is driven from another source, that source MUST be in the range of 2.7V to 5.5V and MUST be alive prior to enabling the LTC1709. Soft-Start/Run Function The RUN/SS pin provides three functions: 1) Run/Shutdown, 2) soft-start and 3) a defeatable short-circuit latchoff timer. Soft-start reduces the input power sources' surge currents by gradually increasing the controller's current limit ITH(MAX). The latchoff timer prevents very short, extreme load transients from tripping the overcurrent latch. A small pull-up current (>5A) supplied to the RUN/ SS pin will prevent the overcurrent latch from operating. The following explanation describes how the functions operate. An internal 1.2A current source charges up the soft-start capacitor, CSS. When the voltage on RUN/SS reaches 1.5V, the controller is permitted to start operating. As the voltage on RUN/SS increases from 1.5V to 3.0V, the internal current limit is increased from 25mV/RSENSE to 75mV/RSENSE. The output current limit ramps up slowly, taking an additional 1.25s/F to reach full current. The output current thus ramps up slowly, reducing the starting surge current required from the input power supply. If RUN/SS has been pulled all the way to ground there is a delay before starting of approximately:
tDELAY =
1.5V CSS = (1.25s / F ) CSS 1.2A
The time for the output current to ramp up is then:
tRAMP =
3V - 1.5V CSS = (1.25s / F ) CSS 1.2A
By pulling the RUN/SS pin below 0.8V the LTC1709 is put into low current shutdown (IQ < 40A). The RUN/SS pins can be driven directly from logic as shown in Figure 6.
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Diode D1 in Figure 6 reduces the start delay but allows CSS to ramp up slowly providing the soft-start function. The RUN/SS pin has an internal 6V zener clamp (see Functional Diagram).
VIN 3.3V OR 5V D1 RUN/SS RSS* D1* CSS CSS INTVCC RSS* RUN/SS *OPTIONAL TO DEFEAT OVERCURRENT LATCHOFF
1709 F06
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Figure 6. RUN/SS Pin Interfacing
Fault Conditions: Overcurrent Latchoff The RUN/SS pin also provides the ability to latch off the controllers when an overcurrent condition is detected. The RUN/SS capacitor, CSS, is used initially to limit the inrush current of both controllers. After the controllers have been started and been given adequate time to charge up the output capacitors and provide full load current, the RUN/ SS capacitor is used for a short-circuit timer. If the output voltage falls to less than 70% of its nominal value after CSS reaches 4.1V, CSS begins discharging on the assumption that the output is in an overcurrent condition. If the condition lasts for a long enough period as determined by the size of CSS, the controller will be shut down until the RUN/SS pin voltage is recycled. If the overload occurs during start-up, the time can be approximated by: tLO1 (CSS * 0.6V)/(1.2A) = 5 * 105 (CSS) If the overload occurs after start-up, the voltage on CSS will continue charging and will provide additional time before latching off: tLO2 (CSS * 3V)/(1.2A) = 2.5 * 106 (CSS) This built-in overcurrent latchoff can be overridden by providing a pull-up resistor, RSS, to the RUN/SS pin as shown in Figure 6. This resistance shortens the soft-start period and prevents the discharge of the RUN/SS capacitor during a severe overcurrent and/or short-circuit condition. When deriving the 5A current from VIN as in the figure, current latchoff is always defeated. Diode connecting this pull-up resistor to INTV CC , as in
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Figure 6, eliminates any extra supply current during shutdown while eliminating the INTVCC loading from preventing controller start-up. Why should you defeat current latchoff? During the prototyping stage of a design, there may be a problem with noise pickup or poor layout causing the protection circuit to latch off the controller. Defeating this feature allows troubleshooting of the circuit and PC layout. The internal short-circuit and foldback current limiting still remains active, thereby protecting the power supply system from failure. A decision can be made after the design is complete whether to rely solely on foldback current limiting or to enable the latchoff feature by removing the pull-up resistor. The value of the soft-start capacitor CSS may need to be scaled with output voltage, output capacitance and load current characteristics. The minimum soft-start capacitance is given by: CSS > (COUT )(VOUT)(10-4)(RSENSE) The minimum recommended soft-start capacitor of CSS = 0.1F will be sufficient for most applications. Phase-Locked Loop and Frequency Synchronization The LTC1709 has a phase-locked loop comprised of an internal voltage controlled oscillator and phase detector. This allows the top MOSFET turn-on to be locked to the rising edge of an external source. The frequency range of the voltage controlled oscillator is 50% around the center frequency fO. A voltage applied to the PLLFLTR pin of 1.2V corresponds to a frequency of approximately 220kHz. The nominal operating frequency range of the LTC1709 is 140kHz to 310kHz. The phase detector used is an edge sensitive digital type which provides zero degrees phase shift between the external and internal oscillators. This type of phase detector will not lock up on input frequencies close to the harmonics of the VCO center frequency. The PLL hold-in range, fH, is equal to the capture range, fC: fH = fC = 0.5 fO (150kHz-300kHz)
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The output of the phase detector is a complementary pair of current sources charging or discharging the external filter network on the PLLFLTR pin. A simplified block diagram is shown in Figure 7. If the external frequency (fPLLIN) is greater than the oscillator frequency f0SC, current is sourced continuously, pulling up the PLLFLTR pin. When the external frequency is less than f0SC, current is sunk continuously, pulling down the PLLFLTR pin. If the external and internal frequencies are the same but exhibit a phase difference, the current sources turn on for an amount of time corresponding to the phase difference. Thus the voltage on the PLLFLTR pin is adjusted until the phase and frequency of the external and internal oscillators are identical. At this stable operating point the phase comparator output is open and the filter capacitor CLP holds the voltage. The LTC1709 PLLIN pin must be driven from a low impedance source such as a logic gate located close to the pin. The loop filter components (CLP, RLP) smooth out the current pulses from the phase detector and provide a stable input to the voltage controlled oscillator. The filter components CLP and RLP determine how fast the loop acquires lock. Typically RLP =10k and CLP is 0.01F to 0.1F.
2.4V RLP 10k CLP
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PHASE DETECTOR
EXTERNAL OSC
PLLFLTR PLLIN
50k
DIGITAL PHASE/ FREQUENCY DETECTOR
OSC
1709 F07
Figure 7. Phase-Locked Loop Block Diagram
Minimum On-Time Considerations Minimum on-time tON(MIN) is the smallest time duration that the LTC1709 is capable of turning on the top MOSFET. It is determined by internal timing delays and the gate charge required to turn on the top MOSFET. Low duty cycle
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applications may approach this minimum on-time limit and care should be taken to ensure that:
tON(MIN) < VOUT VIN f
()
If the duty cycle falls below what can be accommodated by the minimum on-time, the LTC1709 will begin to skip cycles resulting in variable frequency operation. The output voltage will continue to be regulated, but the ripple current and ripple voltage will increase. The minimum on-time for the LTC1709 is generally less than 200ns. However, as the peak sense voltage decreases, the minimum on-time gradually increases. This is of particular concern in forced continuous applications with low ripple current at light loads. If the duty cycle drops below the minimum on-time limit in this situation, a significant amount of cycle skipping can occur with correspondingly larger ripple current and voltage ripple. If an application can operate close to the minimum ontime limit, an inductor must be chosen that has a low enough inductance to provide sufficient ripple amplitude to meet the minimum on-time requirement. As a general rule, keep the inductor ripple current of each phase equal to or greater than 15% of IOUT(MAX) at VIN(MAX). Voltage Positioning Voltage positioning can be used to minimize peak-to-peak output voltage excursion under worst-case transient loading conditions. The open-loop DC gain of the control loop is reduced depending upon the maximum load step specification. Voltage positioning can easily be added to the LTC1709 by loading the ITH pin with a resistive divider having a Thevenin equivalent voltage source equal to the midpoint operating voltage of the error amplifier, or 1.2V (see Figure 8). The resistive load reduces the DC loop gain while maintaining the linear control range of the error amplifier. The worst-case peak-to-peak output voltage deviation due to transient loading can theoretically be reduced to half or alternatively the amount of output capacitance can be reduced for a particular application. A complete explana-
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INTVCC RT2 ITH RT1 RC CC
1709 F08
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LTC1709
Figure 8. Active Voltage Positioning Applied to the LTC1709
tion is included in Design Solutions 10 or the LTC1736 data sheet. (See www.linear-tech.com) Efficiency Considerations The percent efficiency of a switching regulator is equal to the output power divided by the input power times 100%. It is often useful to analyze individual losses to determine what is limiting the efficiency and which change would produce the most improvement. Percent efficiency can be expressed as: %Efficiency = 100% - (L1 + L2 + L3 + ...) where L1, L2, etc. are the individual losses as a percentage of input power. Although all dissipative elements in the circuit produce losses, four main sources usually account for most of the losses in LTC1709 circuits: 1) I2R losses, 2) Topside MOSFET transition losses, 3) INTVCC regulator current and 4) LTC1709 VIN current (including loading on the differential amplifier output). 1) I2R losses are predicted from the DC resistances of the fuse (if used), MOSFET, inductor, current sense resistor, and input and output capacitor ESR. In continuous mode the average output current flows through L and RSENSE, but is "chopped" between the topside MOSFET and the synchronous MOSFET. If the two MOSFETs have approximately the same RDS(ON), then the resistance of one MOSFET can simply be summed with the resistances of L, RSENSE and ESR to obtain I2R losses. For example, if each RDS(ON)=10m, RL=10m, and RSENSE=5m, then the total resistance is 25m. This results in losses ranging from 2% to 8% as the output current increases from 3A to 15A per output stage for a 5V output, or a 3% to 12% loss per output stage for a 3.3V output. Efficiency varies as the inverse square of VOUT for the same external components
LTC1709
APPLICATIO S I FOR ATIO
and output power level. The combined effects of increasingly lower output voltages and higher currents required by high performance digital systems is not doubling but quadrupling the importance of loss terms in the switching regulator system! 2) Transition losses apply only to the topside MOSFET(s), and are significant only when operating at high input voltages (typically 12V or greater). Transition losses can be estimated from: Transition Loss = (1.7) VIN2 IO(MAX) CRSS f 3) INTVCC current is the sum of the MOSFET driver and control currents. The MOSFET driver current results from switching the gate capacitance of the power MOSFETs. Each time a MOSFET gate is switched from low to high to low again, a packet of charge dQ moves from INTVCC to ground. The resulting dQ/dt is a current out of INTVCC that is typically much larger than the control circuit current. In continuous mode, IGATECHG = (QT + QB), where QT and QB are the gate charges of the topside and bottom side MOSFETs. Supplying INTVCC power through the EXTVCC switch input from an output-derived source will scale the VIN current required for the driver and control circuits by the ratio (Duty Factor)/(Efficiency). For example, in a 20V to 5V application, 10mA of INTVCC current results in approximately 3mA of VIN current. This reduces the mid-current loss from 10% or more (if the driver was powered directly from VIN) to only a few percent. 4) The VIN current has two components: the first is the DC supply current given in the Electrical Characteristics table, which excludes MOSFET driver and control currents; the second is the current drawn from the differential amplifier output. VIN current typically results in a small (<0.1%) loss. Other "hidden" losses such as copper trace and internal battery resistances can account for an additional 5% to 10% efficiency degradation in portable systems. It is very important to include these "system" level losses in the design of a system. The internal battery and input fuse resistance losses can be minimized by making sure that CIN has adequate charge storage and a very low ESR at the switching frequency. A 50W supply will typically require a
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minimum of 200F to 300F of output capacitance having a maximum of 10m to 20m of ESR. The LTC1709 2-phase architecture typically halves the input and output capacitance requirement over competing solutions. Other losses including Schottky conduction losses during deadtime and inductor core losses generally account for less than 2% total additional loss. Checking Transient Response The regulator loop response can be checked by looking at the load transient response. Switching regulators take several cycles to respond to a step in DC (resistive) load current. When a load step occurs, VOUT shifts by an amount equal to ILOAD(ESR), where ESR is the effective series resistance of COUT * (ILOAD) also begins to charge or discharge COUT generating the feedback error signal that forces the regulator to adapt to the current change and return VOUT to its steady-state value. During this recovery time VOUT can be monitored for excessive overshoot or ringing, which would indicate a stability problem. The availability of the ITH pin not only allows optimization of control loop behavior but also provides a DC coupled and AC filtered closed loop response test point. The DC step, rise time, and settling at this test point truly reflects the closed loop response. Assuming a predominantly second order system, phase margin and/or damping factor can be estimated using the percentage of overshoot seen at this pin. The bandwidth can also be estimated by examining the rise time at the pin. The ITH external components shown in the Figure 1 circuit will provide an adequate starting point for most applications. The ITH series RC-CC filter sets the dominant pole-zero loop compensation. The values can be modified slightly (from 0.2 to 5 times their suggested values) to optimize transient response once the final PC layout is done and the particular output capacitor type and value have been determined. The output capacitors need to be decided upon because the various types and values determine the loop gain and phase. An output current pulse of 20% to 80% of full-load current having a rise time of <2s will produce output voltage and ITH pin waveforms that will give a sense of the overall loop stability without breaking the feedback loop. The initial output voltage step resulting from the step change in output current may not be within
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LTC1709
APPLICATIO S I FOR ATIO
the bandwidth of the feedback loop, so this signal cannot be used to determine phase margin. This is why it is better to look at the Ith pin signal which is in the feedback loop and is the filtered and compensated control loop response. The gain of the loop will be increased by increasing RC and the bandwidth of the loop will be increased by decreasing CC. If RC is increased by the same factor that CC is decreased, the zero frequency will be kept the same, thereby keeping the phase the same in the most critical frequency range of the feedback loop. The output voltage settling behavior is related to the stability of the closedloop system and will demonstrate the actual overall supply performance. Automotive Considerations: Plugging into the Cigarette Lighter As battery-powered devices go mobile, there is a natural interest in plugging into the cigarette lighter in order to conserve or even recharge battery packs during operation. But before you connect, be advised: you are plugging into the supply from hell. The main battery line in an automobile is the source of a number of nasty potential transients, including load-dump, reverse-battery, and double-battery. Load-dump is the result of a loose battery cable. When the cable breaks connection, the field collapse in the alternator can cause a positive spike as high as 60V which takes several hundred milliseconds to decay. Reverse-battery is just what it says, while double-battery is a consequence of tow truck operators finding that a 24V jump start cranks cold engines faster than 12V. The network shown in Figure 9 is the most straightforward approach to protect a DC/DC converter from the ravages of an automotive power line. The series diode prevents current from flowing during reverse-battery, while the transient suppressor clamps the input voltage during load-dump. Note that the transient suppressor should not conduct during double-battery operation, but must still clamp the input voltage below breakdown of the converter. Although the LT1709 has a maximum input voltage of 36V, most applications will be limited to 30V by the MOSFET BVDSS.
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50A IPK RATING 12V TRANSIENT VOLTAGE SUPPRESSOR GENERAL INSTRUMENT 1.5KA24A
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VIN
LTC1709
1709 F09
Figure 9. Automotive Application Protection
Design Example As a design example, assume VIN = 5V (nominal), VIN = 5.5V (max), VOUT = 1.8V, IMAX = 20A, TA = 70C and f = 300kHz. The inductance value is chosen first based on a 30% ripple current assumption. The highest value of ripple current occurs at the maximum input voltage. Tie the PLLFLTR pin to the INTVCC pin for 300kHz operation. The minimum inductance for 30% ripple current is:
L
VOUT VOUT 1- f( I) VIN 1.8 V 1.8 V 1- (300kHz)(30%)(10A) 5.5V
1.35H
A 1.5H inductor will produce 27% ripple current. The peak inductor current will be the maximum DC value plus one half the ripple current, or 11.4A. The minimum ontime occurs at maximum VIN:
tON(MIN) = VOUT 1.8 V = = 1.1s VINf (5.5V )(300kHz)
The RSENSE resistors value can be calculated by using the maximum current sense voltage specification with some accomodation for tolerances: RSENSE = 50mV 0.004 11.4A
LTC1709
APPLICATIO S I FOR ATIO
The power dissipation on the topside MOSFET can be easily estimated. Using a Siliconix Si4420DY for example; RDS(ON) = 0.013, CRSS = 300pF. At maximum input voltage with Tj (estimated) = 110C at an elevated ambient temperature:
PMAIN =
1.8V (10)2 1+ (0.005)(110C - 25C ) 5.5V
[
(300kHz)= 0.65W
0.013 + 1.7(5.5V ) (10A )(300pF )
2
The worst-case power disipated by the synchronous MOSFET under normal operating conditions at elevated ambient temperature and estimated 50C junction temperature rise is: PSYNC = 5.5V - 1.8 V 10 A 5.5V = 1.29W
( ) (1.48)(0.013)
2
A short-circuit to ground will result in a folded back current of about:
ISC 25mV 1 200ns(5.5V ) = + = 7A 0.004 2 1.5H
The worst-case power disipated by the synchronous MOSFET under short-circuit conditions at elevated ambient temperature and estimated 50C junction temperature rise is:
PSYNC = 5.5V - 1.8V (7A)2 (1.48)(0.013) 5.5V = 630mW
which is less than half of the normal, full-load conditions. Incidentally, since the load no longer dissipates power in the shorted condition, total system power dissipation is decreased by over 99%.
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The duty factor for this application is:
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DF. = .
VO 1.8 V = = 0.36 VIN 5V
Using Figure 4, the RMS ripple current will be:
]
IINRMS = (20A)(0.23) = 4.6ARMS An input capacitor(s) with a 4.6ARMS ripple current rating is required. The output capacitor ripple current is calculated by using the inductor ripple already calculated for each inductor and multiplying by the factor obtained from Figure 3 along with the calculated duty factor. The output ripple in continuous mode will be highest at the maximum input voltage since the duty factor is < 50%. The maximum output current ripple is: VOUT (0.3) at 33%D. F. fL 1.8V ICOUTMAX = 0.3 (300kHz)(1.5H) ICOUT = VOUTRIPPLE = 20m(1.2ARMS ) = 24mVRMS PC Board Layout Checklist When laying out the printed circuit board, the following checklist should be used to ensure proper operation of the LTC1709. These items are also illustrated graphically in the layout diagram of Figure 11. Check the following in your layout: 1) Are the signal and power grounds segregated? The LTC1709 signal ground pin should return to the (-) plate of COUT separately. The power ground returns to the sources of the bottom N-channel MOSFETs, anodes of the Schottky diodes, and (-) plates of CIN, which should have as short lead lengths as possible. 2) Does the LTC1709 VOS+ pin connect to the point of load? Does the LTC1709 VOS- pin connect to the load return? = 1.2ARMS
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LTC1709
APPLICATIO S I FOR ATIO
3) Are the SENSE - and SENSE + leads routed together with minimum PC trace spacing? The filter capacitors between SENSE + and SENSE - pin pairs should be as close as possible to the LTC1709. Ensure accurate current sensing with Kelvin connections at the current sense resistor. 4) Does the (+) plate of CIN connect to the drains of the topside MOSFETs and the (-) plate of CIN to the sources of the bottom MOSFETS as closely as possible? This capacitor provides the AC current to the MOSFETs. Keep the input current path formed by the input capacitor, top and bottom MOSFETs, and the Schottky diode on the same side of the PC board in a tight loop to minimize conducted and radiated EMI. 5) Is the INTVCC 1F ceramic decoupling capacitor connected closely between INTVCC and the PGND pin? This capacitor carries the MOSFET driver peak currents. A small value is recommended to allow placement immediately adjacent to the IC. 6) Keep the switching nodes, SW1 (SW2), away from sensitive small-signal nodes. Ideally the switch nodes should be placed at the furthest point from the LTC1709. 7) Use a low impedance source such as a logic gate to drive the PLLIN pin and keep the lead as short as possible. The diagram in Figure 10 illustrates all branch currents in a 2-phase switching regulator. It becomes very clear after studying the current waveforms why it is critical to keep the high-switching-current paths to a small physical size. High electric and magnetic fields will radiate from these "loops" just as radio stations transmit signals. The output capacitor ground should return to the negative terminal of the input capacitor and not share a common ground path with any switched current paths. The left half of the circuit gives rise to the "noise" generated by a switching regulator. The ground terminations of the sychronous MOSFETs and Schottky diodes should return to the negative plate(s) of the input capacitor(s) with a short isolated PC trace since very high switched currents are present. A separate isolated path from the negative plate(s) of the input capacitor(s) should be used to tie in the IC power ground pin (PGND) and the signal ground pin (SGND). This technique keeps inherent signals generated by high current pulses from taking alternate current paths that have
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finite impedances during the total period of the switching regulator. External OPTI-LOOP compensation allows overcompensation for PC layouts which are not optimized but this is not the recommended design procedure. Simplified Visual Explanation of How a 2-Phase Controller Reduces Both Input and Output RMS Ripple Current A multiphase power supply significantly reduces the amount of ripple current in both the input and output capacitors. The effective input and output ripple frequency is multiplied up by the number of phases used. Figure 11 graphically illustrates the principle. The worst-case RMS ripple current for a single stage design peaks at an input voltage of twice the output voltage. The worst-case RMS ripple current for a two stage design results in peak outputs of 1/4 and 3/4 of input voltage. When the RMS current is calculated, higher effective duty factor results and the peak current levels are divided as long as the currents in each stage are balanced. Refer to Application Note 77 for a detailed description of how to calculate RMS current for the multiphase switching regulator. Figures 3 and 4 help to illustrate how the input and output currents are reduced by using an additional phase. The input current peaks drop in half and the frequency is doubled for this 2-phase converter. The input capacity requirement is thus reduced theoretically by a factor of four! Ceramic input capacitors with their unbeatably low ESR characteristics can be used. Figure 4 illustrates the RMS input current drawn from the input capacitance vs the duty cycle as determined by the ratio of input and output voltage. The peak input RMS current level of the single phase system is reduced by 50% in a 2-phase solution due to the current splitting between the two stages. An interesting result of the 2-phase solution is that the VIN which produces worst-case ripple current for the input capacitor, VOUT = VIN/2, in the single phase design produces zero input current ripple in the 2-phase design.
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LTC1709
APPLICATIO S I FOR ATIO
The output ripple current is reduced significantly when compared to the single phase solution using the same inductance value because the VOUT/L discharge current term from the stage that has its bottom MOSFET on subtracts current from the (VIN - VOUT)/L charging current resulting from the stage which has its top MOSFET on. The output ripple current is:
IRIPPLE =
2VOUT 1 - 2D 1 - D fL 1 - 2D + 1
( )

where D is duty factor.
SW1
D1
VIN RIN CIN
+
SW2
BOLD LINES INDICATE HIGH, SWITCHING CURRENT LINES. KEEP LINES TO A MINIMUM LENGTH.
D2
Figure 10. Instantaneous Current Path Flow in a Multiple Phase Switching Regulator
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The input and output ripple frequency is increased by the number of stages used, reducing the output capacity requirements. When VIN is approximately equal to 2(VOUT) as illustrated in Figures 3 and 4, very low input and output ripple currents result.
L1 RSENSE1 VOUT COUT RL
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L2
RSENSE2
1709 F10
25
LTC1709
APPLICATIO S I FOR ATIO U
DUAL PHASE SW1 V SW2 V IL1 ICOUT IL2 ICIN ICOUT RIPPLE
1709 F11
SW V
ICIN
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SINGLE PHASE
Figure 11. Single and 2-Phase Current Waveforms
LTC1709
PACKAGE DESCRIPTIO U
Dimensions in inches (millimeters) unless otherwise noted.
G Package 36-Lead Plastic SSOP (0.209)
(LTC DWG # 05-08-1640)
12.67 - 12.93* (0.499 - 0.509) 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19
7.65 - 7.90 (0.301 - 0.311)
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 5.20 - 5.38** (0.205 - 0.212) 1.73 - 1.99 (0.068 - 0.078)
0 - 8
0.13 - 0.22 (0.005 - 0.009)
0.55 - 0.95 (0.022 - 0.037)
0.65 (0.0256) BSC
NOTE: DIMENSIONS ARE IN MILLIMETERS *DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.152mm (0.006") PER SIDE **DIMENSIONS DO NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.254mm (0.010") PER SIDE
0.25 - 0.38 (0.010 - 0.015)
0.05 - 0.21 (0.002 - 0.008)
G36 SSOP 1098
Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
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LTC1709
TYPICAL APPLICATIO
1000pF 0.1F INTVCC 100pF 47k 3.3nF 15k 10k 51k 2.7k
9 10 11 12 13 14 1000pF 15 16 17 470pF 18
VDIFFOUT VOS - VOS + SENSE 2
-
BG2 BOOST 2 SW2 TG2 AMPMD
27 26 25 24 23 D4 10 0.22F
+
SGND
PGND
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+
SWITCHING FREQUENCY = 310kHz MI - M4: FAIRCHILD FDS7760A L1 - L2: SUMIDA CEP125-1R5M
Figure 12. 5V Input, 1.8V/20A Power Supply with Active Voltage Positioning
RELATED PARTS
PART NUMBER LTC1438/LTC1439 LTC1438-ADJ LTC1538-AUX LTC1539 LTC1436A-PLL DESCRIPTION Dual Synchronous Controller with Auxiliary Regulator Dual High Efficiency Low Noise Synchronous Step-Down Switching Regulator Dual High Efficiency Low Noise Synchronous Step-Down Switching Regulator High Efficiency Low Noise Synchronous Step-Down Switching Regulator COMMENTS POR, External Feedback Divider Auxiliary Regulator, 5V Standby 5V Standby, POR, Low-Battery, Aux Regulator Adaptive PowerTM Mode, 24-Pin SSOP Constant Frequency, Standby, 5V and 3.3V LDOs Expandable Up to 12 Phases, G-28, Up to 120A Adjustable Output Up to 40A, G-28 500kHz, 25MHz GBW 1.3V VOUT 3.5V (LTC1709-8), 1.1V VOUT 1.85V (LTC1709-9), Current Mode Ensures Accurate Current Sharing, 3.5V VIN 36V 1.3V VOUT 3.5V, Current Mode Ensures Accurate Current Sharing, 3.5V VIN 36V Burst ModeTM Operation, 16-Pin Narrow SSOP, Fault Protection, 3.5V VIN 36V Output Fault Protection, Power Good, GN-24, 3.5V VIN 36V, 0.925V VOUT 2V Dual High Efficiency Low Noise Synchronous Step-Down Switching Regulators POR, Auxiliary Regulator
LTC1628/LTC1628-PG Dual High Efficiency, 2-Phase Synchronous Step-Down Switching Regulator LTC1629/LTC1629-PG PolyPhase High Efficiency Controller LTC1929 LTC1702/LTC1703 LTC1709-7/ LTC1709-8/ LTC1709-9 LTC1708-PG LTC1735 LTC1736 2-Phase High Efficiency Controller Dual High Efficiency, 2-Phase Synchronous Step-Down Switching Regulator High Efficiency, 2-Phase Synchronous Step-Down Switching Regulator with 5-Bit VID and Power Good Indication
Dual High Efficiency, 2-Phase Synchronous Step-Down Switching Regulator with 5-Bit VID and Power Good Indication High Efficiency Synchronous Step-Down Controller High Efficiency Synchronous Step-Down Controller with 5-Bit VID
Adaptive Power and Burst Mode are trademarks of Linear Technology Corporation.
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Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408)432-1900 q FAX: (408) 434-0507 q www.linear-tech.com
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LTC1709 1 2 3 4 5 6 7 8 RUN/SS SENSE 1 + SENSE 1 - EAIN PLLFLTR PLLIN NC ITH NC TG1 SW1 BOOST 1 VIN BG1 EXTVCC INTVCC 36 35 34 33 32 31 30 29 1F,25V D3 10 0.1F GND 47Fx2 4.7F 6.3V 35V 0.22F M1 L1 1.5H 0.004 M2 D1 MBRM 140T3 COUT
+
D2 MBRM 140T3
4x180F 4V VIN 5V TO 28V
SENSE 2 +
M3
M4 0.004
ATTENOUT ATTENIN VID0 VID1
VBIAS VID4 VID3 VID2
22 21 20 19 0.1F
L2 1.5H
VOUT 1.3V TO 3.5V
VID INPUTS
COUT OUTPUT CAPACITORS: PANASONIC EEFUE0G181R D3, D4: CENTRAL CMDSH-3TR
1709 TA02
1709f LT/TP 0500 4K * PRINTED IN USA
(c) LINEAR TECHNOLOGY CORPORATION 1999

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